CST 441 - Logic Synthesis with VHDL

(F)
Lecture Hours: 2
Lab Hours: 3
Credit Hours: 3

This course will show students how to use the hardware description language, VHDL, with hierarchical design techniques to manage a complex design. In this process, students will create a design using the VHDL modeling tools, simulate the design using advanced simulation techniques, synthesize and test the design. Laboratory integral with the course.

Prerequisite: CST 351 or instructor consent