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Apr 25, 2024
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2020-21 University Catalog [ARCHIVED CATALOG]
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CST 441 - Logic Synthesis with VHDL Lecture Hours: 2 Lab Hours: 3 Credit Hours: 3
This course will show students how to use the hardware description language, VHDL, with hierarchical design techniques to manage a complex design. In this process students will create a design using the VHDL modeling tools, simulate the design using advanced simulation techniques, synthesize and test the design. Laboratory integral with the course.
Prerequisite: CST 351 or instructor consent
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